Commit 15585c78 authored by Tuukka Panula's avatar Tuukka Panula
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# Change Log
All notable changes to bmi160 Sensor API will be documented in this file.
## v3.6.0, 04 Aug 2017
#### Added
* Added interfaces for the following features
- FOC
- Manual Offset compensation
- Offset compenation value update to NVM
## v3.5.0, 13 Apr 2017
#### Added
* Self-test feature for accel and gyro added
## v3.4.0, 31 Mar 2017
#### Added
* Auxiliary sensor interface in auto-mode(data-mode) support is implemented
## v3.3.0, 31 Mar 2017
#### Added
* Extracting of gyro data from FIFO is implemented.
## v3.2.1, 15 Mar 2017
#### Changed
* Aux init made compatible for all auxillary sensors.
## v3.2.0, 09 Mar 2017
#### Added
* Reading FIFO data and extracting of accel data from FIFO implemented.
* FIFO FULL Interrupt implemented only for Accel data.
## v3.1.0, 15 Feb 2017
#### Changed
* Condition for gyro BW corrected in order to set for all BW modes.
* Interrupt Active High level setting handled.
* Existing step detector code corrected for recommended settings.
* Disabling of step detector and step counter has been removed in low-g interrupt.
#### Added
* Error code implemented, if input parameter is out of range or invalid.
* Source of data (filter & prefilter) setting handled for slope, no-motion, tap, sig, high-g & Low-g interrupt.
* Error handling of Pre-filter data & Interrupt is done in low power mode.
* Burst write handled for low & suspended power mode.
* Auxiliary read & write implemented in order to read the BMM150 data.
* Interrupt disable mechanism added.
//----------------------------------------------------------------------------
// Description: This file contains definitions specific to the ADS1293.
// All the ADS1293 registers are defined as well as some common masks
// for these registers.
//
// MSP430/ADS1293 Interface Code Library v1.0
//
// Vishy Natarajan
// Texas Instruments Inc.
// February 2012
// Built with CCE Version: 4.2 and IAR Embedded Workbench Version: 5.3x
//------------------------------------------------------------------------------
// Change Log:
//------------------------------------------------------------------------------
// Version: 1.00
// Comments: Initial Release Version
//------------------------------------------------------------------------------
#ifndef HEADER_FILE_TI_ADS1293_H
#define HEADER_FILE_TI_ADS1293_H
/************************************************************
* TI ADS1293 REGISTER SET ADDRESSES
************************************************************/
#define TI_ADS1293_CONFIG_REG (0x00) /* Main Configuration */
#define TI_ADS1293_FLEX_CH1_CN_REG (0x01) /* Flex Routing Swich Control for Channel 1 */
#define TI_ADS1293_FLEX_CH2_CN_REG (0x02) /* Flex Routing Swich Control for Channel 2 */
#define TI_ADS1293_FLEX_CH3_CN_REG (0x03) /* Flex Routing Swich Control for Channel 3 */
#define TI_ADS1293_FLEX_PACE_CN_REG (0x04) /* Flex Routing Swich Control for Pace Channel */
#define TI_ADS1293_FLEX_VBAT_CN_REG (0x05) /* Flex Routing Swich Control for Battery Monitoriing */
#define TI_ADS1293_LOD_CN_REG (0x06) /* Lead Off Detect Control */
#define TI_ADS1293_LOD_EN_REG (0x07) /* Lead Off Detect Enable */
#define TI_ADS1293_LOD_CURRENT_REG (0x08) /* Lead Off Detect Current */
#define TI_ADS1293_LOD_AC_CN_REG (0x09) /* AC Lead Off Detect Current */
#define TI_ADS1293_CMDET_EN_REG (0x0A) /* Common Mode Detect Enable */
#define TI_ADS1293_CMDET_CN_REG (0x0B) /* Commond Mode Detect Control */
#define TI_ADS1293_RLD_CN_REG (0x0C) /* Right Leg Drive Control */
#define TI_ADS1293_WILSON_EN1_REG (0x0D) /* Wilson Reference Input one Selection */
#define TI_ADS1293_WILSON_EN2_REG (0x0E) /* Wilson Reference Input two Selection */
#define TI_ADS1293_WILSON_EN3_REG (0x0F) /* Wilson Reference Input three Selection */
#define TI_ADS1293_WILSON_CN_REG (0x10) /* Wilson Reference Input Control */
#define TI_ADS1293_REF_CN_REG (0x11) /* Internal Reference Voltage Control */
#define TI_ADS1293_OSC_CN_REG (0x12) /* Clock Source and Output Clock Control */
#define TI_ADS1293_AFE_RES_REG (0x13) /* Analog Front-End Frequency and Resolution */
#define TI_ADS1293_AFE_SHDN_CN_REG (0x14) /* Analog Front-End Shutdown Control */
#define TI_ADS1293_AFE_FAULT_CN_REG (0x15) /* Analog Front-End Fault Detection Control */
#define TI_ADS1293_AFE_DITHER_EN_REG (0x16) /* Enable Dithering in Signma-Delta */
#define TI_ADS1293_AFE_PACE_CN_REG (0x17) /* Analog Pace Channel Output Routing Control */
#define TI_ADS1293_ERROR_LOD_REG (0x18) /* Lead Off Detect Error Status */
#define TI_ADS1293_ERROR_STATUS_REG (0x19) /* Other Error Status */
#define TI_ADS1293_ERROR_RANGE1_REG (0x1A) /* Channel 1 Amplifier Out of Range Status */
#define TI_ADS1293_ERROR_RANGE2_REG (0x1B) /* Channel 1 Amplifier Out of Range Status */
#define TI_ADS1293_ERROR_RANGE3_REG (0x1C) /* Channel 1 Amplifier Out of Range Status */
#define TI_ADS1293_ERROR_SYNC_REG (0x1D) /* Synchronization Error */
#define TI_ADS1293_DIGO_STRENGTH (0x1F) /* Digital output drive strength */
#define TI_ADS1293_R2_RATE_REG (0x21) /* R2 Decimation Rate */
#define TI_ADS1293_R3_RATE1_REG (0x22) /* R3 Decimation Rate for Channel 1 */
#define TI_ADS1293_R3_RATE2_REG (0x23) /* R3 Decimation Rate for Channel 2 */
#define TI_ADS1293_R3_RATE3_REG (0x24) /* R3 Decimation Rate for Channel 3 */
#define TI_ADS1293_P_DRATE_REG (0x25) /* 2x Pace Data Rate */
#define TI_ADS1293_DIS_EFILTER_REG (0x26) /* ECG Filter Disable */
#define TI_ADS1293_DRDYB_SRC_REG (0x27) /* Data Ready Pin Source */
#define TI_ADS1293_SYNCOUTB_SRC_REG (0x28) /* Sync Out Pin Source */
#define TI_ADS1293_MASK_DRDYB_REG (0x29) /* Optional Mask Control for DRDYB Output */
#define TI_ADS1293_MASK_ERR_REG (0x2A) /* Mask Error on ALARMB Pin */
#define TI_ADS1293_ALARM_FILTER_REG (0x2E) /* Digital Filter for Analog Alarm Signals */
#define TI_ADS1293_CH_CNFG_REG (0x2F) /* Configure Channel for Loop Read Back Mode */
#define TI_ADS1293_DATA_STATUS_REG (0x30) /* ECG and Pace Data Ready Status */
#define TI_ADS1293_DATA_CH1_PACE_H_REG (0x31) /* Channel1 Pace Data High [15:8] */
#define TI_ADS1293_DATA_CH1_PACE_L_REG (0x32) /* Channel1 Pace Data Low [7:0] */
#define TI_ADS1293_DATA_CH2_PACE_H_REG (0x33) /* Channel2 Pace Data High [15:8] */
#define TI_ADS1293_DATA_CH2_PACE_L_REG (0x34) /* Channel2 Pace Data Low [7:0] */
#define TI_ADS1293_DATA_CH3_PACE_H_REG (0x35) /* Channel3 Pace Data High [15:8] */
#define TI_ADS1293_DATA_CH3_PACE_L_REG (0x36) /* Channel3 Pace Data Low [7:0] */
#define TI_ADS1293_DATA_CH1_ECG_H_REG (0x37) /* Channel1 ECG Data High [23:16] */
#define TI_ADS1293_DATA_CH1_ECG_M_REG (0x38) /* Channel1 ECG Data Medium [15:8] */
#define TI_ADS1293_DATA_CH1_ECG_L_REG (0x39) /* Channel1 ECG Data Low [7:0] */
#define TI_ADS1293_DATA_CH2_ECG_H_REG (0x3A) /* Channel2 ECG Data High [23:16] */
#define TI_ADS1293_DATA_CH2_ECG_M_REG (0x3B) /* Channel2 ECG Data Medium [15:8] */
#define TI_ADS1293_DATA_CH2_ECG_L_REG (0x3C) /* Channel2 ECG Data Low [7:0] */
#define TI_ADS1293_DATA_CH3_ECG_H_REG (0x3D) /* Channel3 ECG Data High [23:16] */
#define TI_ADS1293_DATA_CH3_ECG_M_REG (0x3E) /* Channel3 ECG Data Medium [15:8] */
#define TI_ADS1293_DATA_CH3_ECG_L_REG (0x3F) /* Channel3 ECG Data Low [7:0] */
#define TI_ADS1293_REVID_REG (0x40) /* Revision ID */
#define TI_ADS1293_DATA_LOOP_REG (0x50) /* Loop Read Back Address */
// Useful definitions
#define ADS1293_READ_BIT (0x80)
#define ADS1293_WRITE_BIT (0x7F)
#endif // HEADER_FILE_TI_ADS1293_H
//3lead version
//----------------------------------------------------------------------------
// Description: This file contains the initialization values for the
// ADS1293 registers.
//
// MSP430/ADS1293 Interface Code Library v1.0
//
// Vishy Natarajan
// Texas Instruments Inc.
// October 2011
// Built with CCE Version: 4.2 and IAR Embedded Workbench Version: 5.3x
//------------------------------------------------------------------------------
// Change Log:
//------------------------------------------------------------------------------
// Version: 1.00
// Comments: Initial Release Version
//------------------------------------------------------------------------------
#ifndef HEADER_FILE_TI_ADS1293_REGISTER_SETTINGS_H
#define HEADER_FILE_TI_ADS1293_REGISTER_SETTINGS_H
/************************************************************
* TI ADS1293 REGISTER SET INITIALIZATION VALUES
************************************************************/
#define TI_ADS1293_CONFIG_REG_VALUE (0x00) /* Main Configuration */
#define TI_ADS1293_FLEX_CH1_CN_REG_VALUE (0x11) /* Flex Routing Swich Control for Channel 1 */
#define TI_ADS1293_FLEX_CH2_CN_REG_VALUE (0x12) /* Flex Routing Swich Control for Channel 2 */
#define TI_ADS1293_FLEX_CH3_CN_REG_VALUE (0x00) /* Flex Routing Swich Control for Channel 3 */
#define TI_ADS1293_FLEX_PACE_CN_REG_VALUE (0x00) /* Flex Routing Swich Control for Pace Channel */
#define TI_ADS1293_FLEX_VBAT_CN_REG_VALUE (0x00) /* Flex Routing Swich Control for Battery Monitoriing */
#define TI_ADS1293_LOD_CN_REG_VALUE (0x08) /* Lead Off Detect Control */
#define TI_ADS1293_LOD_EN_REG_VALUE (0x00) /* Lead Off Detect Enable */
#define TI_ADS1293_LOD_CURRENT_REG_VALUE (0x00) /* Lead Off Detect Current */
#define TI_ADS1293_LOD_AC_CN_REG_VALUE (0x00) /* AC Lead Off Detect Current */
#define TI_ADS1293_CMDET_EN_REG_VALUE (0x07) /* Common Mode Detect Enable */
#define TI_ADS1293_CMDET_CN_REG_VALUE (0x00) /* Commond Mode Detect Control */
#define TI_ADS1293_RLD_CN_REG_VALUE (0x04) /* Right Leg Drive Control */
#define TI_ADS1293_WILSON_EN1_REG_VALUE (0x00) /* Wilson Reference Input one Selection */
#define TI_ADS1293_WILSON_EN2_REG_VALUE (0x00) /* Wilson Reference Input two Selection */
#define TI_ADS1293_WILSON_EN3_REG_VALUE (0x00) /* Wilson Reference Input three Selection */
#define TI_ADS1293_WILSON_CN_REG_VALUE (0x00) /* Wilson Reference Input Control */
#define TI_ADS1293_REF_CN_REG_VALUE (0x00) /* Internal Reference Voltage Control */
#define TI_ADS1293_OSC_CN_REG_VALUE (0x04) /* Clock Source and Output Clock Control */
#define TI_ADS1293_AFE_RES_REG_VALUE (0x00) /* Analog Front-End Frequency and Resolution */
#define TI_ADS1293_AFE_SHDN_CN_REG_VALUE (0x24) /* Analog Front-End Shutdown Control */
#define TI_ADS1293_AFE_FAULT_CN_REG_VALUE (0x00) /* Analog Front-End Fault Detection Control */
#define TI_ADS1293_AFE_DITHER_EN_REG_VALUE (0x00) /* Enable Dithering in Signma-Delta */
#define TI_ADS1293_AFE_PACE_CN_REG_VALUE (0x00) /* Analog Pace Channel Output Routing Control */
//#define TI_ADS1293_ERROR_LOD_REG_VALUE (0x00) /* Lead Off Detect Error Status */
//#define TI_ADS1293_ERROR_STATUS_REG_VALUE (0x72) /* Other Error Status */
//#define TI_ADS1293_ERROR_RANGE1_REG_VALUE (0x12) /* Channel 1 Amplifier Out of Range Status */
//#define TI_ADS1293_ERROR_RANGE2_REG_VALUE (0x12) /* Channel 1 Amplifier Out of Range Status */
//#define TI_ADS1293_ERROR_RANGE3_REG_VALUE (0x36) /* Channel 1 Amplifier Out of Range Status */
//#define TI_ADS1293_ERROR_SYNC_REG_VALUE (0x00) /* Synchronization Error */
#define TI_ADS1293_R2_RATE_REG_VALUE (0x02) /* R2 Decimation Rate */
#define TI_ADS1293_R3_RATE1_REG_VALUE (0x02) /* R3 Decimation Rate for Channel 1 */
#define TI_ADS1293_R3_RATE2_REG_VALUE (0x02) /* R3 Decimation Rate for Channel 2 */
#define TI_ADS1293_R3_RATE3_REG_VALUE (0x00) /* R3 Decimation Rate for Channel 3 */
#define TI_ADS1293_P_DRATE_REG_VALUE (0x00) /* 2x Pace Data Rate for all channels */
#define TI_ADS1293_DIS_EFILTER_REG_VALUE (0x00) /* ECG Filters Disabled */
#define TI_ADS1293_DRDYB_SRC_REG_VALUE (0x08) /* Data Ready Pin Source */
#define TI_ADS1293_SYNCOUTB_SRC_REG_VALUE (0x00) /* Sync Out Pin Source */
#define TI_ADS1293_MASK_DRDYB_REG_VALUE (0x00) /* Optional Mask Control for DRDYB Output */
#define TI_ADS1293_MASK_ERR_REG_VALUE (0x00) /* Mask Error on ALARMB Pin */
#define TI_ADS1293_ALARM_FILTER_REG_VALUE (0x33) /* Digital Filter for Analog Alarm Signals */
#define TI_ADS1293_CH_CNFG_REG_VALUE (0x30) /* Configure Channel for Loop Read Back Mode */
//#define TI_ADS1293_DATA_STATUS_REG_VALUE (0x00) /* ECG and Pace Data Ready Status */
//#define TI_ADS1293_DATA_CH1_PACE_H_REG_VALUE (0x00) /* Channel1 Pace Data High [15:8] */
//#define TI_ADS1293_DATA_CH1_PACE_L_REG_VALUE (0x00) /* Channel1 Pace Data Low [7:0] */
//#define TI_ADS1293_DATA_CH2_PACE_H_REG_VALUE (0x00) /* Channel2 Pace Data High [15:8] */
//#define TI_ADS1293_DATA_CH2_PACE_L_REG_VALUE (0x00) /* Channel2 Pace Data Low [7:0] */
//#define TI_ADS1293_DATA_CH3_PACE_H_REG_VALUE (0x00) /* Channel3 Pace Data High [15:8] */
//#define TI_ADS1293_DATA_CH3_PACE_L_REG_VALUE (0x00) /* Channel3 Pace Data Low [7:0] */
//#define TI_ADS1293_DATA_CH1_ECG_H_REG_VALUE (0x00) /* Channel1 ECG Data High [23:16] */
//#define TI_ADS1293_DATA_CH1_ECG_M_REG_VALUE (0x00) /* Channel1 ECG Data Medium [15:8] */
//#define TI_ADS1293_DATA_CH1_ECG_L_REG_VALUE (0x00) /* Channel1 ECG Data Low [7:0] */
//#define TI_ADS1293_DATA_CH2_ECG_H_REG_VALUE (0x00) /* Channel2 ECG Data High [23:16] */
//#define TI_ADS1293_DATA_CH2_ECG_M_REG_VALUE (0x00) /* Channel2 ECG Data Medium [15:8] */
//#define TI_ADS1293_DATA_CH2_ECG_L_REG_VALUE (0x00) /* Channel2 ECG Data Low [7:0] */
//#define TI_ADS1293_DATA_CH3_ECG_H_REG_VALUE (0x00) /* Channel3 ECG Data High [23:16] */
//#define TI_ADS1293_DATA_CH3_ECG_M_REG_VALUE (0x00) /* Channel3 ECG Data Medium [15:8] */
//#define TI_ADS1293_DATA_CH3_ECG_L_REG_VALUE (0x00) /* Channel3 ECG Data Low [7:0] */
#define TI_ADS1293_REVID_REG_VALUE (0x40) /* Revision ID */
#define TI_ADS1293_DATA_LOOP_REG_VALUE (0x50) /* Loop Read Back Address */
// Useful definitions
#define ADS1293_START_CONV (0x01) // Start Conversion Bit
#endif // HEADER_FILE_TI_ADS1293_REGISTER_SETTINGS_H
/*
* ads1293.c
*
* Authors: juanko, jmtuom
*/
#include "trc_master_config.h"
#if ECG_ENABLED
#include <string.h>
#include "ads1293.h"
#include "globals.h"
#include "Heartache_HW_config.h"
#include "../FIFO/fifo.h"
#include "SDCard/sdcard.h"
#include "Power.h"
#include "./RTC/RTC.h"
#include "nrf_drv_gpiote.h"
#include "BLE/ble_stuff.h"
fifo_t Ecg_fifo_instance;
uint8_t EcgFifo[ECG_FIFO_SIZE]; //The actual buffer
#define ADS_RANGE 0
channel_t ads_channels[ECG_CHANNELS] = {
{"Lead_I",true,267,24,ADS_RANGE,true},
#if (ECG_CHANNELS > 1)
{"Lead_II",true,267,24,ADS_RANGE,true},
#endif
#if (ECG_CHANNELS > 2)
#if ECG_LEAD_V1_ENABLED
{"Lead_V",true,267,24,ADS_RANGE,true}
#else
{"Lead_III",true,267,24,ADS_RANGE,true}
#endif
#endif
};
#if DEBUG_ADS
uint32_t ADS_Events_Handled = 0;
#endif
/**@brief Event handler for ECG.
* @note If ECG FIFO gets almost full, it will set event pending-flag, which will be handled here
* @param[in] Sensor ID
* @todo Remove double buffering! Use ECG FIFO directly when creating SDCard-packet
* @retval TRC_SUCCESS Successful operation.
* @return A propagated error code.
*/
TRC_Error_t ecg_evt_handler(uint8_t sensorID, uint8_t param) {
UNUSED_PARAMETER(param);
TRC_Error_t err_code = TRC_SUCCESS;
ads1293_data_t EcgBuffer[ECG_BUFFER_SIZE];
threebytes_t tmp_buffer[ECG_BUFFER_SIZE]; //Note: assuming same sample rate for all channels
uint32_t count;
err_code = trc_fifo_get(&Ecg_fifo_instance,(uint8_t *)EcgBuffer,ECG_FIFO_WM);
if (err_code) {
if (err_code == FIFO_ERROR_FIFO_OVERREAD) {
//Never mind, this is probably caused by ecg fifo overflow -> resetted after that
sensors[sensorID].evt_pending = false;
return TRC_SUCCESS;
} else {
return (FIFO_ERROR_ECG_FIFO_BASE+err_code);
}
}
#ifdef SDCARD_ENABLED
if (flags.SDCard_mounted && Holter_state_current == HOLTER_STATE_LOGGING) {
//Create separate data packages for each channel
//assuming same sampling rate for all channels - need to fix later...
if (sensors[sensorID].channels[0]->enabled) {
for (count=0; count < (ECG_BUFFER_SIZE); count++) {
tmp_buffer[count] = EcgBuffer[count].ch1;
}
err_code = SDcard_add_to_buffer((0x80+sensorID), ECG_CH1_ID, sensors[sensorID].last_evt_timestamp, (uint8_t*)tmp_buffer, ECG_BUFFER_SIZE*ECG_BYTES_PER_CHANNEL);
if (err_code) {
APP_ERROR_CHECK(err_code);
}
}
#if (ECG_CHANNELS > 1)
if (sensors[sensorID].channels[1]->enabled) {
for (count=0; count < ECG_BUFFER_SIZE; count++) {
tmp_buffer[count] = EcgBuffer[count].ch2;
}
err_code = SDcard_add_to_buffer((0x80+sensorID), ECG_CH2_ID, sensors[sensorID].last_evt_timestamp, (uint8_t*)tmp_buffer, ECG_BUFFER_SIZE*ECG_BYTES_PER_CHANNEL);
if (err_code) {
APP_ERROR_CHECK(err_code);
}
}
#endif //>1 ECG_CHANNELS
#if (ECG_CHANNELS > 2)
if (sensors[sensorID].channels[2]->enabled) {
for (count=0; count < ECG_BUFFER_SIZE; count++) {
tmp_buffer[count] = EcgBuffer[count].ch3;
}
err_code = SDcard_add_to_buffer((0x80+sensorID), ECG_CH3_ID, sensors[sensorID].last_evt_timestamp, (uint8_t*)tmp_buffer, ECG_BUFFER_SIZE*ECG_BYTES_PER_CHANNEL);
if (err_code) {
APP_ERROR_CHECK(err_code);
}
}
#endif //>2 ECG_CHANNELS
}
#endif //SDCARD_ENABLED
sensors[sensorID].evt_pending = false;
//Enable ADS interrupt again
//nrf_drv_gpiote_in_event_enable(sensors[sensorID].int_pin, true);
#if DEBUG_ADS
ADS_Events_Handled++;
#endif
return err_code;
}
static TRC_Error_t TI_ADS1293_SPIWriteReg(uint8_t hw_addr, uint8_t addr, uint8_t value){
TRC_Error_t err_code = TRC_SUCCESS;
//hw_addr carries bus id [7:6] and slave select pin number [5:0]
spi_master_hw_instance_t bus_id = (spi_master_hw_instance_t) ((hw_addr & 0xC0) >> 6);
u8 ss_pin = (hw_addr & 0x3F);
uint8_t txbuff[2];
txbuff[0] = addr;
txbuff[1] = value;
err_code = spi_master_send_recv(bus_id, txbuff, 2, NULL, 0, ss_pin);
return err_code;
}
static uint8_t TI_ADS1293_SPIReadReg(uint8_t hw_addr, uint8_t addr){
TRC_Error_t err_code = TRC_SUCCESS;
//hw_addr carries bus id [7:6] and slave select pin number [5:0]
spi_master_hw_instance_t bus_id = (spi_master_hw_instance_t) ((hw_addr & 0xC0) >> 6);
u8 ss_pin = (hw_addr & 0x3F);
uint8_t tx_array[2];
uint8_t rx_array[2];
tx_array[0] = addr |0x80; //set msb of address byte = read bit
tx_array[1] = 0xFF; //Dummy
err_code = spi_master_send_recv(bus_id, tx_array, 1, rx_array, 2, ss_pin);
UNUSED_VARIABLE(err_code);
return rx_array[1]; //should take pointer to read buf instead and return just error code...
}
//Combine single read and streamread to a single function?
static TRC_Error_t TI_ADS1293_SPIStreamReadReg(uint8_t hw_addr, uint8_t * rxbuffer, uint8_t count){
TRC_Error_t err_code = TRC_SUCCESS;
uint32_t temp = 0;
//hw_addr carries bus id [7:6] and slave select pin number [5:0]
spi_master_hw_instance_t bus_id = (spi_master_hw_instance_t) ((hw_addr & 0xC0) >> 6);
u8 ss_pin = (hw_addr & 0x3F);
uint8_t local_rx_buffer[1+ECG_CHANNELS*ECG_BYTES_PER_CHANNEL]; // +1 because we need to skip dummy rx byte received during tx
uint8_t tx_buffer = TI_ADS1293_DATA_LOOP_REG | 0x80; //set msb of address byte = read bit
err_code = spi_master_send_recv(bus_id, &tx_buffer, 1, local_rx_buffer, count+1, ss_pin);
if (bus_id == SPI_MASTER_0) {
while(flags.SPI_0_Busy) { temp++; }
} else {
while(flags.SPI_1_Busy) { temp++; }
}
for (uint8_t i = 0; i < count; i++) {
*(rxbuffer+i) = local_rx_buffer[i+1];
}
return err_code;
}
static TRC_Error_t TI_ADS1293_WriteRegSettings_2lead(uint8_t sensorID) {
TRC_Error_t err_code = TRC_SUCCESS;
#if DEBUG_ADS
uint8_t read_buf;
#endif
//Get hw addr from sensor struct
u8 bus_id = sensors[sensorID].bus_id <<6;
u8 bus_addr = sensors[sensorID].bus_addr; //not enough! I2C addresses are 7-bit!
u8 hw_addr = bus_id+bus_addr;
#define ECG_OFFSET 0x798000 //NOTE: Depends on settings below ... move this to somewhere else..and make it a variable..
static const u8 config_table[] = {
#if ECG_LEADS_IN_CORNERS
//ECG-leads in corners
TI_ADS1293_FLEX_CH1_CN_REG, 0x15, // reg 0x01, 00 010 101: Positive terminal : In2(LA), negative: In5(RA) -> LA-RA = Lead I
TI_ADS1293_FLEX_CH2_CN_REG, 0x1D, // reg 0x02, 00 011 101: Positive terminal : In3(LL), negative: In5(RA) -> LL-RA = Lead II
#if ECG_LEAD_V1_ENABLED
TI_ADS1293_FLEX_CH3_CN_REG, 0x0E, // reg 0x03, 00 001 110: Positive terminal : In1(V1), negative: In6, internal (WCT) -> V1-WCT = Lead V
TI_ADS1293_WILSON_EN1_REG, 0x05, // xxxx x 101 Wilson Reference Input one Selection, input 5 (RA)
TI_ADS1293_WILSON_EN2_REG, 0x02, // xxxx x 010 Wilson Reference Input two Selection, input 2 (LA)
TI_ADS1293_WILSON_EN3_REG, 0x03, // xxxx x 011 Wilson Reference Input three Selection, input 3 (LL)
TI_ADS1293_WILSON_CN_REG, 0x01, // Wilson Reference Input Control: connect internally to in6
#else
TI_ADS1293_FLEX_CH3_CN_REG, 0x1A, // reg 0x03, 00 011 010: Positive terminal : In3(LL), negative: In2(LA) -> LL-LA = Lead III
#endif
TI_ADS1293_RLD_CN_REG, 0x04, // reg 0x0C 0 0 00 0 100: Right leg drive control -> in4
#if (ECG_CHANNELS == 1)
TI_ADS1293_CMDET_EN_REG, 0x12, // reg 0x0A, 00 010010 Enable common mode detector on pins in2, in5
#endif
#if (ECG_CHANNELS == 2)
TI_ADS1293_CMDET_EN_REG, 0x16, // reg 0x0A, 00 010110 Enable common mode detector on pins in2, in3, in5
#endif
#if (ECG_CHANNELS == 3)
TI_ADS1293_CMDET_EN_REG, 0x16, // reg 0x0A, 00 010110 Enable common mode detector on pins in2, in3, in5
#endif
#endif //ECG_LEADS_IN_CORNERS
#if ECG_WITH_CONNECTOR
//6-pin smd conn. adapter
/* pin mappings:
1 ra . in6
2 la . in1
3 ll . in5
4 rl . in2
5 nc . in4
6 nc . in3
*/
//ACHTUNG! in6 used for wilson reference in 5-lead configuration, must re-route!
TI_ADS1293_FLEX_CH1_CN_REG, 0x0E, // reg 0x01, 00 001 110: Positive terminal : In1(LA), negative: In6(RA) -> LA-RA = Lead I
TI_ADS1293_FLEX_CH2_CN_REG, 0x2E, // reg 0x02, 00 101 110: Positive terminal : In5(LL), negative: In6(RA) -> LL-RA = Lead II
#if ECG_LEAD_V1_ENABLED
//input routing for 5 lead set-up here
#else
TI_ADS1293_FLEX_CH3_CN_REG, 0x29, // reg 0x03, 00 101 001: Positive terminal : In5(LL), negative: In1(LA) -> LL-LA = Lead III
#endif
TI_ADS1293_RLD_CN_REG, 0x02, // reg 0x0C 0 0 00 0 010: Right leg drive control powered on, -> in2 = RLD
#if (ECG_CHANNELS == 1)
TI_ADS1293_CMDET_EN_REG, 0x21, // reg 0x0A, 00 100001 Enable common mode detector on pins in1, in6
#endif
#if (ECG_CHANNELS == 2)
TI_ADS1293_CMDET_EN_REG, 0x31, // reg 0x0A, 00 110001 Enable common mode detector on pins in1, in5, in6
#endif
#if (ECG_CHANNELS == 3)
#if ECG_LEAD_V1_ENABLED
//TO BE CHANGED WHEN PIN-OUT KNOWN
TI_ADS1293_CMDET_EN_REG, 0x31, // reg 0x0A, 00 110001 Enable common mode detector on pins in1, in5, in6
#else
TI_ADS1293_CMDET_EN_REG, 0x31, // reg 0x0A, 00 110001 Enable common mode detector on pins in1, in5, in6
#endif
#endif
#endif //ECG_WITH_CONNECTOR
#if ECG_EXT_CLOCK
//TI_ADS1293_OSC_CN_REG, 0x06, // reg 0x12, xxxx x 110, external oscillator, output to digital
TI_ADS1293_OSC_CN_REG, 0x04, // HW BUG! Clock should be fed to CLK-pin, not XTAL2
#else //Use internal oscillator w/ crystal
TI_ADS1293_OSC_CN_REG, 0x04, // reg 0x12, xxxx x 100, crystal, output to digital
#endif
TI_ADS1293_DIGO_STRENGTH, 0x00, // reg 0x1F, xxxx xx00; Low drive mode. No practical impact to power, but reduces EMI a bit
#if (ECG_CHANNELS == 1)
TI_ADS1293_AFE_SHDN_CN_REG, 0x36, // reg 0x14, Shut down unused ch3 and ch2 paths - use this in 1 ch mode
#endif
#if (ECG_CHANNELS == 2)
TI_ADS1293_AFE_SHDN_CN_REG, 0x24, // reg 0x14, Shut down unused ch3 path - use this in 2 ch mode
#endif
//TI_ADS1293_DIS_EFILTER_REG, 0x07, // reg 0x26, Disable ecg filter for channels 1,2,3
TI_ADS1293_DRDYB_SRC_REG, 0x08, // reg 0x27, Data ready driven by channel 1 ecg
TI_ADS1293_CH_CNFG_REG, 0x70, // reg 0x2F 0 111 000 0: Enable loop-back read mode for ch1-ch3
//TI_ADS1293_CH_CNFG_REG, 0x30, // reg 0x2F 0 111 000 0: Enable loop-back read mode for ch1&ch2
#if HI_RES_ECG
/* 267Hz ODR, 55Hz BW */
/* RMS noise: 1.18uV */
TI_ADS1293_AFE_RES_REG,0x3F, // reg 0x13, HiRes -mode & 204.8kHz for all the channels
TI_ADS1293_P_DRATE_REG,0x07, // reg 0x25, Pace data rate for channels 1,2,3: double (R1=2)
TI_ADS1293_R2_RATE_REG, 0x04, // reg 0x21, decimate by 6 (R2=6)
TI_ADS1293_R3_RATE1_REG, 0x40, // reg 0x22, decimate by 64 (R3=64)
TI_ADS1293_R3_RATE2_REG, 0x40, // reg 0x23, decimate by 64 (R3=64)
TI_ADS1293_R3_RATE3_REG, 0x40 // reg 0x24, decimate by 64 (R3=64)
#else //LOW_RES
/* 267Hz ODR, 55Hz BW */
/* RMS noise: 1.71uV */
TI_ADS1293_AFE_RES_REG,0x00, // reg 0x13, LoRes -mode & 102.4kHz for all the channels
TI_ADS1293_P_DRATE_REG,0x00, // reg 0x25, Pace data rate for channels 1,2,3: standard (R1=4)
TI_ADS1293_R2_RATE_REG, 0x08, // reg 0x21, decimate by 8 (R2=8)
TI_ADS1293_R3_RATE1_REG, 0x08, // reg 0x22, decimate by 12 (R3=12)
TI_ADS1293_R3_RATE2_REG, 0x08, // reg 0x23, decimate by 12 (R3=12)
TI_ADS1293_R3_RATE3_REG, 0x08 // reg 0x24, decimate by 12 (R3=12)
#endif // HI/LO-RES
//other options;
//high-res, 102kHz SDM, standard pace rate: noise: 1.48uV RMS
//low power, 102kHz SDM, standard pace rate: noise: 1.71uV RMS
//high-res, 102kHz SDM, double pace rate: noise: 1.47uV RMS
//low power, 102kHz SDM, double pace rate: noise: 1.70uV RMS