Commit 4e1702eb authored by Philipp Oleynik's avatar Philipp Oleynik
Browse files

Argh.

parent e3568bfc
......@@ -287,6 +287,8 @@ class Sixs:
"""
if thlevel == 1:
channel = self.lut[list(map(int, 63 - side6bit)), list(map(int, core6bit))]
elif thlevel == 2:
channel = self.lut[list(map(int, 63 - side6bit)), list(map(int, core6bit))]
else:
channel = self.lut[63 - side6bit, core6bit]
return channel
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